1. Field of the Invention
The present invention relates to a ferroelectric memory, an more particularly to a ferroelectric memory having a memory cell transistor and a ferroelectric capacitor both formed on a semiconductor substrate for memory retention.
2. Description of the Related Art
In recent years, active technical developments have been made on a ferroelectric memory having a ferroelectric film of spontaneous polarization property as the capacitive insulating film. This ferroelectric memory has a feature of being capable of storing information by the polarization of the ferroelectric capacitor formed on a semiconductor substrate. FIG. 4 shows a sectional view of an example of the unit cell memory constituting a conventional ferroelectric memory. As shown in FIG. 4, n.sup.+ diffusion layers 8 as source/drain regions are formed in the surface regions of a p type silicon substrate 1, and also a gate electrode 7 is formed on the p type silicon substrate via a gate insulating film; thereby, a field effect transistor (which is a cell transistor) is constituted. A bit line 10 made of Al is connected to one of the diffusion layers 8 as source/drain regions, of the field effect transistor.
On the field effect transistor is formed, via an interconnection insulating film, a ferroelectric capacitor constituted by a lower electrode 3, a ferroelectric film 4 and an upper electrode 5. The upper electrode 5 is connected to the other diffusion layer 8 as source/drain region, of the field effect transistor via a wiring layer 6. The ferroelectric film 4 is made of PZT (PbZr.sub.x Ti.sub.1-x O.sub.3), SBT (SrBi.sub.2 Ta.sub.2 O.sub.9) or the like. The lower electrode and the upper electrode are made of an oxidation-resistant noble metal (e.g. Pt) or a conductive oxide (e.g. RuO.sub.2) because annealing in an oxidizing atmosphere is often necessary for the formed ferroelectric capacitor in order to stabilize the thin ferroelectric film of the capacitor. As the wiring layer 6, there is used, for example, a multilayered film consisting of a Ti layer, a TiN layer and an Al layer because the wiring layer 6 are required to be superior in fine processability, adhesivity to Si or SiO.sub.2 and resistivity (i.e. low resistivity).
An equivalent circuit of this memory cell is shown in FIG. 5. A memory cell MC is constituted by the in-series connection of a field effect transistor Tr and a ferroelectric capacitor Cf. The gate electrode of the field effect transistor Tr is connected to a word line WL; one of the source/drain regions is connected to a bit line BL; and the other source/drain region is connected to one of the electrodes of the ferroelectric capacitor Cf. The other electrode of the ferroelectric capacitor Cf is connected to a plate line PL. Generally, the word line WL functions also as the gate electrode of the field effect transistor Tr, and the plate line PL functions also as the lower electrode of the ferroelectric capacitor.
The memory cell MC shown in FIG. 5 is arranged in a matrix form and constitutes a large-scale non-volatile memory.
Next, the process for producing a conventional memory cell shown in FIG. 4 is explained with reference to FIG. 6. FIGS. 6(a) to 6(c) are sectional views showing the steps of the process for producing a conventional memory cell. A ferroelectric capacitor comprising a lower electrode 3, a ferroelectric film 4 and an upper electrode 5 is formed on an interconnection insulating film formed on a silicon substrate 1 having a semiconductor integrated circuit (e.g. memory cell transistors) embedded therein; and a protective film 9 is formed thereon [FIG. 6(a)]. As shown in FIG. 6(b), contact holes are formed which communicate with the upper electrode of the capacitor and also with the diffusion layers of the field effect transistor. Then, as shown in FIG. 6(c), wiring layers are formed to connect one of the diffusion layers of the field effect transistor to the upper electrode of the capacitor and also to form a bit line. Thereafter, a heat treatment is conducted at a temperature higher than 300.degree. C. This heat treatment is an essential step for reduction in contact resistance of transistor, stabilization of threshold volatage, removal of damage applied to ferroelectric capacitor during LSI production process, etc.
In the conventional memory cell, however, there has been a problem that the above heat treatment incurs a substantial reduction in residual polarization intensity of ferroelectric capacitor, which leads to significant deterioration of the memory retention and data-rewriting life of non-volatile memory. The reason for the problem is that the substance (e.g. titanium) constituting the wiring layer diffuses through the upper electrode along the grain boundaries, reaches the ferroelectric film and reacts chemically with the film.
The same problem appears also when a protective film is formed on a memory cell having a structure shown in FIG. 4. That is, at the time when a silicon nitride (Si.sub.3 N.sub.4) film is formed according to a conventional method (e.g. plasma CVD at a substrate temperature of about 300 to 400.degree. C.), the ferroelectric capacitor is deteriorated and the resulting ferroelectric memory has very low reliability.